 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| elan microelectronics corp. no. 12 , innovation 1 st rd., science - based industrial park hsin chu city, taiwan, r.o.c. tel: (03) 5639977 fax: (03) 5780617 EPV6200 vfd controller version 1.2
EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 1 version history specification revision history version content release date EPV6200 1.0 initial version 200 4 / 3 / 30 1.1 r evise error describe 2004/04/06 user application note (before using this chip, take a loo k at the following description note, it includes important messages.) 1. there are some undefined bits in the registers. the values in these bits are unpredicted. these bits are not allowed to use. we use the symbol ? - ? in the spec to recognize them. 2. you will see some names for the register bits definitions. some name will be appear ed very frequently in the whole spec. the following describes the meaning for the register?s definitions such as bit type, bit name, bit number and so on. 7 6 5 4 3 2 1 0 rab7 rab6 bab5 rab4 rab2 rab0 r/w - 0 r/w - 0 r-1 r/w - 1 r r/w bit type bit name bit number read/write (default value=0) read/write (default value=1) read only (w/o default value) read/write (w/o default value) page0 ra register name and its page - rab1 (undefined) not allowed to use r-0 read only (default value=0) read only (default value=1) EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 2 i . general description the EPV6200 is an 8 - bit risc type vfd controller with low power, high speed cmos technology. this integrated single chip has an on_chip watchdog timer (wdt), one time program ming rom (otp) , data ram, programm able real time clock/counter, internal interrupt, power down mode, built - in four - wire spi, ir detector and high voltage output for vfd application . ii . feature cpu ?e operating voltage : 2.2v~5.5v at main clk less then 3.582mhz. main clk(hz): 3.582m ~ 17.91m ?e 4 k x 13 on chip program rom. ?e 256 x 8 on chip data ram ?e 16 level stack for subroutine nesting ?e 8 - bit real time clock/counter (tcc) ?e 8 - bit counters : counter1,counter3,counter4,counter5 ?e 16 - bit counters : counter 2 ?e on - chip watchdog timer (wdt) ?e 99.9 h single instruction cycle commands ?e four modes (main clock ca n be programmed from 447.829k to 17.91 mhz generated by internal pll) mode cpu status main clock 32.768khz clock status sleep mode turn off turn off turn off idle mode turn off turn off turn on green mode turn on turn off turn on normal mode turn on tur n on turn on ?e 8 level normal mode frequency : 447.8 29 k , 895. 658 k , 1.79 1 m , 3.58 2 m , 7.16 5 m , 10.747m , 14.3 31 m , 17.91m hz.. ?e input port interrupt function ?e 1 2 interrupt source , 5 external (ir , int1~int4 ) , 8 internal ( spi,tcc,counter1~5) ?e dual clocks operation (internal pll main clock , external 32.768khz) spi ?e serial interface for clock, data input, data output, strobe pins. gpio ?e gpio 9 port(8 bit) : general purpose input/output; led output ?e gpio c port(8 bit) : general purpose input/output for switch and key scanning(12x4 matrixs) vfd ?e many display modes. (9 - segment & 19 - digit to 20 - segment & 8 - digit) ?e many display modes, can be programmed ?e no external resistor necessary for driver outputs.(p - ch open - drain + pull - down resistor output) por ?e 2.0v power - on voltage detector reset package ?e 52 - pin die or 52 - pin qfp iii . application dvd - r/w, dvd recorder , dvd combo vfd controller EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 3 v . functional block diagram segment driver/ grid driver/ high breakdown driver mcu otp data ram pll real time clock timer serial data interface osc gpio din clk stb osci osco / reset vddx3 vss vee dout gpio9[0:7] 8 gpioc[0:7] 8 gr1 ? gr8 8 gr9/sg20 ? gr16/sg13 8 gr17/sg12/ks12 ? gr19/sg10/ks10 3 sg9/ks9 ? sg5/ks5 5 sg4/ks4 ? sg1/ks1 4 ir pllc avdd fig.2a block diagram data & control bus data ram control sleep and wakeup on i/o port oscillator timing control xin xout pllc r1(tcc) wdt timer prescaler general ram r4 interrupt control rom instruction register instruction decoder r2 r3 r5 stack alu spi ioc5 r5 port5 (hv) p54~p57 ioc6 r6 port6 (hv) p60~p67 ioc7 r7 port7 (hv) p70~p77 ioc8 r8 port8 (hv) p80~p87 ioc9 r9 port9 p90~p97 iocc rc portc pc0~pc7 fig.2b block diagram EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 4 port hv port hv port hv - p60 sg5/ks5 p70 gr16/sg13 - p61 sg6/ks6 p71 gr15 sg14 - p62 sg7/ks7 p72 gr14/sg15 - p63 sg8/ks8 p73 gr13/sg16 p5 4 sg1/ks1 p64 sg9/ks9 p74 gr12/sg17 p55 sg2/ks2 p65 gr19/sg10/ks10 p75 gr11/sg18 p56 sg3/ks3 p66 gr18/sg11/ks11 p76 gr10/sg19 p57 sg4/ks4 p67 gr17/sg12/ks12 p77 gr9/sg20 port hv port gpio port gpio p80 gr8 p90 gpio90/led0/ir pc0 gpioc0/key1 p81 gr7 p91 gpio91/led1/int1 pc1 gpioc1/key2 p82 gr6 p92 gpio92/led2/int2 pc2 gpioc2/key3 p83 gr5 p93 gpio93/led3/int3 pc3 gpioc3/key4 p84 gr4 p94 gpio94/led4/int4 pc4 gpioc4/stb p85 gr3 p95 gpio95/led5 pc5 gpioc5/clk p86 gr2 p96 gpio96/led6 pc6 gpioc6/dout p87 gr1 p97 gpio97/led7 pc7 gpioc7/ din table .2c ports mapping for hv and gpio EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 5 vii . functional descript ions vii .1 operational registers register configuration r page registers addr r page0 r page1 r page2 00 indirect addressing 01 tcc 02 pc 03 page, status 04 ram bank, rsr 05 port5 output data program rom page 06 port6 ou tput data spi data buffer 07 port7 output data counter1 data 08 port8 output data data ram address counter2 lb data 09 port 9 i/o data data ram data buffer counter2 hb data 0 a pll, main clock,wdte counter3 data 0b port9 pull high counter4 data 0c portc i/o data portc pull high counter5 data 0d interrupt flag 0e interrupt flag, wake - up control 0f interrupt flag 10 16 bytes : common registers 1f 20 bank0~bank3 : common registers 3f (32x8 for each bank) ioc page registe rs addr ioc page0 ioc page1 00 01 02 03 04 05 port5 switch 06 07 08 clock source(cn 2 ,cn 1 ) prescaler(cn 2 ,cn 1 ) 09 port 9 i/o control clock source(cn 4 ,cn 3 ) prescaler(cn 4 ,cn 3 ) 0a clock source(cn 5 ) prescaler(cn 5 ) 0b 0c portc i/o control portc switch 0d interrupt mask 0e interrupt mask 0f interrupt mask EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 6 vii .2 operational register detail description r0 (indirect addressing register) r0 is not a physically implemented register. it is used as indirect addressin g pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). example: mov a, @0x20 ;store a address at r4 for indirect addressing mov 0x04, a mov a, @0xaa ;write data 0xaa to r20 at bank0 through r0 mov 0x 00, a r1 (tcc) tcc data buffer. increased by 16.384khz or by the instruction cycle clock (controlled by cont register). written and read by the program as any other register. r2 (program counter) the structure is depicted in fig.3. generates 4 k 13 extern al rom addresses to the relative programming instruction codes. "jmp" instruction allows the direct loading of the low 10 program counter bits. "call" instruction loads the low 10 bits of the pc, pc+1, and then push into the stack. "ret'' ("retl k", "reti" ) instruction loads the program counter with the contents at the top of stack. "mov r2, a" allows the loading of an address from the a register to the pc, and the ninth and tenth bits are cleared to "0''. "add r2,a" allows a relative address be added to th e current pc, and contents of the ninth and tenth bits are cleared to "0''. fig.3 program counter organization "tbl" allows a relative address added to the current pc, and contents of the ninth and tenth bits don't change. the most significant bit (a10~a13) will be loaded with the contents of bit ps0~ps3 in the status register (r5 page 1 ) upon the execution of a "jmp'', "call'', "add r2, a'', or "mov r2, a'' instruction. if an interrupt is triggered, program rom will jump to address 0x08 at page0. the cpu will store acc, r3 status and r5 page automatically, and they will be restored after instruction reti. r3 (status, page selection) (status flag, page selection bits) 7 6 5 4 3 2 1 0 rpage1 rpage0 iocpage t p z dc c r/w - 0 r/w - 0 r/w - 0 r r r/w r/w r/w bit 0(c) : carry flag bit 1(dc) : auxiliary carry flag bit 2(z) : zero flag bit 3(p) : power down bit pc a13 a12 a11 a10 a9 a8 a7~a0 0000 page0 0000~03ff 0001 page1 0400~07ff 0011 page3 0c 00~0fff 0010 page2 0800~0bff stack1 stack2 stack3 stack4 stack5 stack6 stack7 stack8 stack9 stack10 stack11 stack12 stack13 stack14 stack15 stack16 call and interrupt ret retl reti acc,r3,r5(page) r5(page) store restore EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 7 set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. bit 4(t) : time - out bit set to 1 by the "slep" and "wdtc" command, or during power up and reset to 0 by wdt timeout. event t p remark wdt wake up from sleep mode 0 0 wdt time out (not sleep mode) 0 1 /reset wake up from sleep 1 0 power up 1 1 low pulse on /reset x x x : don't care bit 5(iocpage) : change ioc5 ~ ioce to another page 0/1 ioc page0 / ioc page1 bit 6 , bit 7 (rpage0 ~ rpage1) : change r5 ~ r c to another page please refer to vii.1 operational registers for detail register configuration. (rpage1,rpage0) r page # selected (0,0) r page 0 (0,1) r page 1 (1, x ) r page 2 r4 (ram selection for common registers r20 ~ r3f)) (ram selection register) 7 6 5 4 3 2 1 0 rb1 rb0 rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 r/w - 0 r/w - 0 r/w r/w r/w r/w r/w r/w bit 0 ~ bit 5 (rsr0 ~ rsr5) : indirect addressing f or common registers r20 ~ r3f rsr bits are used to select up to 32 registers (r20 to r3f) in the indirect addressing mode. bit 6 ~ bit 7 (rb0 ~ rb1) : bank selection bits for common registers r20 ~ r3f these selection bits are used to determine which bank is activated among the 4 banks for 32 register (r20 to r3f).. please refer to vii.1 operational registers for details. r5 (port5 output data, program page selection) page0 (port5 output data register for hv ) 7 6 5 4 3 2 1 0 p57 p56 p55 p54 - - - - w - 0 w - 0 w - 0 w - 0 - - - - page 1 (program rom page register) 7 6 5 4 3 2 1 0 ad9 ad8 - - ps3 ps2 ps1 ps0 r r - - r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 3 (ps0 ~ ps3) : program page selection bits ps 3 ps2 ps1 ps0 program memory page (address) 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 user can use page instruction to change page to maintain program page by user. and the program page is maintained by emc's complier. it will change user's program by inserting instructions within program. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 8 r6 (port6 output data) page0 (port6 output data register for hv ) 7 6 5 4 3 2 1 0 p67 p66 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 page2 (spi data buffer) 7 6 5 4 3 2 1 0 spib7 spib6 spib5 spib4 spib3 spib2 spib1 spib0 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (spib0 ~ spib7) : spi data buffer if you write data to this register, the data will write to spiw register. if you read this data, it will read the data from spir register. please refer to figure5 read/write buffer shift register stb clk din dout rbf_int stb_int fig. 5 r7 (port7 output data , counter1 data page 0 (port7 output data register for hv ) 7 6 5 4 3 2 1 0 p77 p76 p75 p74 p73 p72 p71 p70 page 2 (counter 1 data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn17 cn16 cn15 cn14 cn13 cn12 cn11 cn1 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 9 bit 0 ~ bit 7 (cn10 ~ cn17) : counter1's buffer that user can read and write. counter1 is a 8 - bit up - counter with 8 - bit prescaler that user can use r7 page2 to preset and read the counter.(write preset) after a interruption , it will reload the preset value. r8 (port8 output data, data ram address) , counter2_lb data page 0 (port8 output data register for hv ) 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 w - 0 page 1 (da ta ram address register) 7 6 5 4 3 2 1 0 ram_a7 ram_a6 ram_a5 ram_a4 ram_a3 ram_a2 ram_a1 ram_a0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 7 (ram_a0 ~ ram_a7) : data ram address page 2 (counter2 low byte data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn27 cn26 cn25 cn24 cn23 cn22 cn21 cn20 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (cn20 ~ cn27) : counter2 _lb 's buffer that user can read and write. counter2 is a 16 - bit up - counter with 8 - bit prescaler that user can use r8 p age2 to preset and read the counter.(write preset) after a interruption, it will reload the preset value. r9 (port9 i/o data, data ram data buffer) ,counter2_hb data page0 (port9 i/o data register) 7 6 5 4 3 2 1 0 p9 7 p9 6 p9 5 p94 p93 p92 p91 p90 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (p90 ~ p9 7 ) : 8 - bit port9(0~ 7 ) i/o data register user can use ioc register to define input or output each bit , and to define the pull high condition . bit 0: 1. p90: be defined as input/output 2. led0: be defined as outp ut 3. ir input: be defined as input and ir is enable (when iocf bit7 is set to 1) bit 1~bit4: 1. p91~p94: be defined as input/output 2. led1~led4: be defined as output 3. int1~int4: be defined as input bit 5~bit7: 1. p95~p97: be defined as input/output 2. led5~led7: b e defined as output page 1 (data ram data register) 7 6 5 4 3 2 1 0 ram_d7 ram_d6 ram_d5 ram_d4 ram_d3 ram_d2 ram_d1 ram_d0 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (ram_d0 ~ ram_d7) : data ram?s data page 2 (counter2 high byte data register) bit 7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 10 cn2 15 cn2 14 cn2 13 cn2 12 cn2 11 cn2 10 cn2 9 cn2 8 r/w r/w r/w r/w r/w r/w r/w r/w bit 0 ~ bit 7 (cn2 8 ~ cn2 15 ) : counter2 _hb 's buffer that user can read and write. counter2 is a 16 - bit up - counter with 8 - bit prescaler tha t user can use r 9 page2 to preset and read the counter.(write preset) after a interruption, it will reload the preset value. ra (pll, main clock selection, watchdog timer) , counter3 data page0 (pll enable bit, main clock selection bits, watchdog timer e nable bit) 7 6 5 4 3 2 1 0 idle pllen clk2 clk1 clk0 - - wdten r/w - 0 r/w - 0 r/w - 0 r/w - 1 r/w - 1 r/w - 0 bit 0(wdten) : watch dog control bit user can use wdtc instruction to clear watch dog counter. the counter 's clock source is 32768/2 hz. if the prescal er assigns to tcc. watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. if the prescaler assigns to wdt, the time of time out will be more times depending on the ratio of prescaler. 0/1 disable/enable bit 1~bit 2 : unused bit 3 ~ bit 5 (clk0 ~ clk 2) : main clock selection bits user can choose different frequency of main clock by clk1 and clk2. all the clock selection is list below. pllen clk2 clk1 clk0 sub clock main clock cpu clock 1 0 0 0 32.768khz 447.829khz 447.829khz (normal mode) 1 0 0 1 3 2.768khz 895.658khz 895.658khz (normal mode) 1 0 1 0 32.768khz 1.791mhz 1.791mhz (normal mode) 1 0 1 1 32.768khz 3.582mhz 3.582mhz (normal mode) 1 1 0 0 32.768khz 7.165mhz 7.165mhz (normal mode) 1 1 0 1 32.768khz 10.747mhz 10.747mhz (normal mode) 1 1 1 0 32.768khz 14.331mhz 14.331mhz (normal mode) 1 1 1 1 32.768khz 17.91mhz 17.91mhz (normal mode) 0 don?t care don?t car e don?t care 32.768khz don?t care 32.768khz (green mode) bit 6(pllen) : pll's power control bit which is cpu mode control register 0/1 disable pll/enable pll if enable pll, cpu will operate at normal mode (high frequency). otherwise, it will run at green mode (low frequency, 32768 hz). sub-clock 32.768khz switch 0 1 system clock pll circuit 447.8293khz ~17.9132mhz enpll clk2 ~ clk0 fig. 6 the relation between 32.768khz and pll bit 7(idle) : sleep mode or idle mode control after using "slep" instruction. 0/1 sleep mode/idle mode. this bit will decide slep instruction which mode to go. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 11 the status after wake - up and the wake - up sources list as the table below. wakeup signal sleep mode idle mode ra (7,6)=(0,0) + slep ra(7,6)=(1,0) + slep tcc time out iocf bit0=1 no function (1) wake - up (2) jump to slep next instruction counter1 time out iocf bit1=1 no function (1) wake - up (2) jump to slep next instruction counter2 time out iocf bit2=1 no functi on (1) wake - up (2) jump to slep next instruction counter 3 time out ioc d bit0=1 no function (1) wake - up (2) jump to slep next instruction counter 4 time out ioc d bit 1 =1 no function (1) wake - up (2) jump to slep next instruction counter 5 time out ioc d bit 2 = 1 no function (1) wake - up (2) jump to slep next instruction port90(ir function) ioc f bit 3 = 1 reset and jump to address 0 (1) wake - up (2) jump to slep next instruction wdt time out reset and jump to address 0 (1) wake - up (2) next instruction port c (0~3) (k ey1~key4) re page0 bit3 or bit4 or bit5 or bit6 = 1 reset and jump to address 0 (1) wake - up (2) jump to slep next instruction port 9 (1~ 4 ) iocf bit4 or bit5 or bit6 =1 or bit7=1 reset and jump to address 0 (1) wake - up (2) jump to slep next instruction EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 12 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/ w - 0 bit 0 ~ bit 7 (cn 4 0 ~ cn 4 7) : counter 4 's buffer that user can read and write. counter 4 is a 8 - bit up - counter with 8 - bit prescaler that user can use rb page 2 to preset and read the counter.(write preset) after a interruption , it will reload the pr eset value. rc (portc i/o data , counter 5 data ) page 0 i/o data buffer /serial signal 7 6 5 4 3 2 1 0 pc 7 pc 6 pc 5 pc 4 pc3 pc2 pc1 pc0 r/w r/w r/w r/w r/w r/w r/w r/w bit0~bit3: 1. pc0~pc3: be defined as input/output 2. key1~key4: be defined as keyscan inpu t bit4: 1. pc4 be defined as input/output 2. stb : serial strobe signal bit5: 1. pc5 be defined as input/output 2. clk: serial clock signal bit6: 1. pc6 be defined as input/output 2. sdo : serial data out bit7: 1. pc7 be defined as input/output 2. sdi : serial data in page1 (port c, pull high ) 7 6 5 4 3 2 1 0 p hc7 p hc6 p hc5 p hc4 p hc3 p hc2 p hc1 p hc 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 7 (ph c 0 ~ ph c7 ) : port c bit0~bit 7 pull high control register 0 disable pull high functi on. 1 enable pull high function page2 (counter 5 data register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cn 5 7 cn 5 6 cn 5 5 cn 5 4 cn 5 3 cn 5 2 cn 5 1 cn 5 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 7 (cn 5 0 ~ cn 5 7) : counter 5 's buffer that user c an read and write. counter 5 is a 8 - bit up - counter with 8 - bit prescaler that user can use rc page 2 to preset and read the counter.(write preset) after a interruption , it will reload the preset value. rd ( interrupt flag,) page 0 (interrupt flagss regist er) 7 6 5 4 3 2 1 0 - - - - - cnt 5 cnt 4 cnt3 - - - - - r/w - 0 r/w - 0 r/w - 0 "1" means interrupt request, "0" means non - interrupt bit 0 (cnt 3 ) : counter 3 timer overflow interrupt flag set when counter 3 timer overflows. bit 1(cnt 4 ) : counter 4 timer overflow i nterrupt flag set when counter 4 timer overflows. bit 2(cnt 5 ) : counter 5 timer overflow interrupt flag set when counter 5 timer overflows. re (interrupt flag s , wake - up) page0 (interrupt flag s , wake - up control bits) 7 6 5 4 3 2 1 0 - rbf - stb /wup c 3 /wup c 2 /wu pc 1 /wup c 0 - r/w - 0 - r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 (/wup c 0) : port c 0 wake - up control, 0/1 disable/enable p c 0 pin wake - up function EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 13 bit 1 (/wup c 1) : port c 1 wake - up control, 0/1 disable/enable p c 1 pin wake - up function bit 2 (/wup c 2) : port c 2 wake - up control, 0/1 disable/enable p c 2 pin wake - up function bit 3 (/wup c 3) : port c 3 wake - up control, 0/1 disable/enable p c 3 pin wake - up function bit 4(stb) : spi data transfer starting interrupt. while the stb signal goes low, it will issue this in terrupt. bit 5 ( - ): - bit 6 (rbf) : spi data transfer complete interrupt if spi's rbf signal has a rising edge signal (rbf set to "1" when transfer data completely), cpu will set this bit. bit 7( - ) : - rf (interrupt flags) page0( interrupt status register) 7 6 5 4 3 2 1 0 int4 int3 int2 int1 ir cnt2 cnt1 tcif r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 "1" means interrupt request, "0" means non - interrupt bit 0(tcif) : tcc timer overflow interrupt flag set when tcc timer overflows. bit 1(cnt1) : counter 1 timer overflow interrupt flag set when counter1 timer overflows. bit 2(cnt2) : counter2 timer overflow interrupt flag set when counter2 timer overflows. bit 3(ir) : external int pin interrupt flag if port 9 0 has a falling edge / rising edge (controlled by cont register) trigger signal, cpu will set this bit. bit 4(int1) : external int1 pin interrupt flag if port 9 1 has a falling edge trigger signal, cpu will set this bit. bit 5(int2) : external int2 pin interrupt flag if port 9 2 has a falling edge trigger si gnal, cpu will set this bit. bit 6 : (int3) : external int3 pin interrupt flag if port 9 3 has a falling edge trigger signal, cpu will set this bit. bit 7( int4 ) : external ir interrupt flag if port 94 has a falling edge trigger signal, cpu will set this bit. trigger edge as the table signal trigger tcc time out counter1 time out counter2 time out counter 3 time out counter 4 time out counter 5 time out ir falling rising edge int1 falling edge int2 falling edge int 3 falling edge int4 falling edge r 10 ~r3f (general purpose register) r 1 0~r1f , r 2 0~r3f (banks 0 ~ 3) : all are general purpose registers. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 14 vii .3 special purpose registers a (accumulator) internal data transfer, or instruction operand holding it's not an addressable regist er. cont (control register) 7 6 5 4 3 2 1 0 p 9 0eg int ts retbk pab psr2 psr1 psr0 bit 0 ~ bit 2 (psr0 ~ psr2) : tcc/wdt prescaler bits psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1 :64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3(pab) : prescaler assignment bit 0/1 tcc/wdt bit 4(retbk) : return value backup control for interrupt routine 0/1 disable/enable when this bit is set to 1, the cpu will store acc,r3 status and r5 page 1 automatically after an interrupt is triggered. and it will be restored after instruction reti. when this bit is set to 0, the user need to store acc, r3 and r5 page 1 in user program. bit 5(ts) : tcc signal source 0 internal instruction cycle clock 1 16.384khz bit 6 (int) : int enable flag 0 interrupt masked by disi or hardware interrupt 1 interrupt enabled by eni/reti instructions bit 7(p 9 0eg) : interrupt edge type of p 9 0 0 p 9 0 's interruption source is a rising edge signal. 1 p 9 0 's interru ption source is a falling edge signal. cont register is readable (contr) and writable (contw). tcc and wdt : there is an 8 - bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time. an 8 bit counter is available for tcc or wdt determined by the status of the bit 3 (pab) of the cont register. see the prescaler ratio in cont register. fig.17 depicts the circuit diagram of tcc/wdt. both tcc and prescaler will be cleared by instructions which write to tcc each time. the prescaler will be cleared by the wdtc and slep instructions, when assigned to wdt mode. the prescaler will not be cleared by slep instructions, when assigned to tcc mode. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 15 fig. 7 block diagram of tcc wdt ioc 5 (port5 switches) page 1 7 6 5 4 3 2 1 0 p 5 7s p 5 6s p 5 5s p 5 4s r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 4~ bit 7 (p 54 s ~p57s ) : port5 i/o direction control register 0 put the relative i/o pin as output hv 1 put the relative i/o pin into high impedance ioc8 page1 ( clock sou rce and prescaler for counter1 and counter2 ) 7 6 5 4 3 2 1 0 cnt2s c2_psc2 c2_psc1 c2_psc0 cnt1s c1_psc2 c1_psc1 c1_psc0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 2 (c1_psc0 ~ c1_psc2) : counter1 prescaler ratio c1_psc2 c1_psc1 c1_psc0 counter1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3(cnt1s) : counter1 clock source 0/1 16.384khz/system clock bit 4 ~ bit 6 (c2_psc0 ~ c2_psc2) : counter2 prescaler ratio c2_psc2 c2_psc1 c2_psc0 counter2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 16.38khz EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 16 1 1 1 1:256 bit 7(cnt2s) : counter2 clock source 0/1 16.384khz/system clock ioc9 (port9 i/o control , c lock source and prescaler for counter3 and counter4 ) page0 (port9 i/o control register) 7 6 5 4 3 2 1 0 ioc9 7 ioc9 6 ioc9 5 ioc94 ioc9 3 ioc9 2 ioc9 1 ioc9 0 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 bit 0 ~ bit 7 (ioc90 ~ ioc9 7 ) : port9(0~ 7 ) i/o direction control register 0 put the relative i/o pin as output 1 put the relative i/o pin into high impedance page1 ( clock source and prescaler for counter3 and counter 4 ) 7 6 5 4 3 2 1 0 cnt4s c4_psc2 c4_psc1 c4_psc0 cnt3s c3_psc2 c3_psc1 c3_psc0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ b it 2 (c3_psc0 ~ c3_psc2) : counter3 prescaler ratio c3_psc2 c3_psc1 c3_psc0 counter3 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3(cnt3s) : counter3 clock source 0/1 16.384khz/system clock bit 4 ~ b it 6 (c4_psc0 ~ c4_psc2) : counter4 prescaler ratio c4_psc2 c4_psc1 c4_psc0 counter4 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 7(cnt4s) : counter4 clock source 0/1 16.384khz/system clock ioca pa ge1 ( c lock source and prescaler for counter5 ) 7 6 5 4 3 2 1 0 - - - - cnt5s c5_psc2 c5_psc1 c5_psc0 - - - - r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ bit 2 (c5_psc0 ~ c5_psc2) : counter5 prescaler ratio c5_psc2 c5_psc1 c5_psc0 counter5 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 17 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3(cnt5s) : counter5 clock source 0/1 16.384khz/system clock iocc (portc i/o control) page0 (portc i/o control register) 7 6 5 4 3 2 1 0 iocc 7 iocc 6 iocc 5 iocc 4 iocc 3 iocc 2 iocc 1 iocc 0 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 bit 0 ~ bit 7 (iocc0 ~ iocc 7 ) : portc(0~ 7 ) i/o direction control register 0 put the relative i/o pin as output 1 put the relative i/o pin into high impedance page 1 (port c switches) 7 6 5 4 3 2 1 0 p c7 s p c 6s p c 5s p c4 s - - - - r/w - 1 r/w - 1 r/w - 1 r/w - 1 - - - - bit 4 (p c4 s) : select stb or i/o port c4 pin 0 p c4 (i/o portc4) pin is selected 1 stb pin is selected bit 5 (p c5 s) : select clk or i/o port c5 pin 0 p c5 (i/o portc 5 ) pin is selected 1 cl k pin is selected bit 6 (p c6 s) : select dout or i/o port c6 pin 0 p c6 (i/o portc 6 ) pin is selected 1 dout pin is selected (n - channel,open - drain) bit 7 (p c7 s) : select din or i/o port c7 pin 0 p c7 (i/o portc 7 ) pin is selected 1 din pin is selected ioc d ( interrupt mask , prescaler of cn3 ~ cn5 ) page0 (interrupt mask) 7 6 5 4 3 2 1 0 - - - - - cnt 5 cnt 4 cnt3 - - - - - r/w - 0 r/w - 0 r/w - 0 bit 0 ~ 3 : interrupt enable bit 0 disable interrupt 1 enable interrupt ioce (interrupt mask ) page0 (interrupt ma sk) 7 6 5 4 3 2 1 0 - rbf - stb - - - - - r/w - 0 - r/w - 0 - - - - bit 4( stb ): stb goes low interrupt mask. 0/1 disable/enable interrupt bit 5 ( - ): - 0/1 disable/enable interrupt bit 6 (rbf) : spi?s rbf interrupt mask 0/1 disable/enable interrupt io cf (interrupt mask ) page0 (interrupt mask register) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 18 int4 int 3 int 2 int 1 ir cnt2 cnt1 tcif r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 bit 0 ~ 7 : interrupt enable bit 0 disable interrupt 1 enable interrupt EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 19 ioce bit6 = 1 and ?eni (jump to address 8 at page0) (jump to address 8 at page0) stb ioce bit 4 = 1 and ?eni no function interru pt (jump to address 8 at page0) interrupt (jump to address 8 at page0) EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 20 vii.5 reset the reset can be caused by (1) power on reset (2) wdt timeout. (if enabled and in green or normal mode) (3) /reset pin pull low once the reset occurs, the following functions are performed. the oscillator is running, or will be started. the program counter (r2) is set to all "0". when power on, the upper 3 bits of r3 and the upper 2 bits of r4 are cleared. the watchdog timer and prescaler counter are cleared. the watchdog timer is disabled. the cont register is set to all "1" the other register (bit 7 ~ bit 0) default values are as follows. operation registers : address r register page0 r register page1 r register page2 r register page3 ioc register page0 ioc register page1 0x4 00xxxxxx 0x5 0000xxxx xxxx0000 00000000 0x6 00000000 xxxxxxxx 0x7 00000000 00000000 xxxxxxxx 0x8 00000000 00000000 xxxxxxxx 00000000 0x9 00 00 0000 xxxxxxxx xxxxxxxx 111 11111 00000000 0xa 00011xx0 xxxxxxxx xxxxxxxx 00000000 0xb 00000000 00000000 xxxxxxxx x 1111111 x 00000 0 0 0 xc 1011xxxx 00000000 xxxxxxxx 1111 xxxx 1111xxxx 0xd xxxxx000 xxxxx000 0xe x 0000000 x000xxxx 0xf 00000000 0 0 000000 vii.6 wake - up the controller has two types of sleep mode for power saving : (1) sleep mode, ra(7) = 0 + "slep" instruction the controller will turn off all the cpu and crystal. other circuit with power control like key tone control or pll control (which has enable register), user has to turn it off by software. (2) idle mode, ra(7) = 1 + "slep" instruction. the controller wil l turn off the cpu , but the crystal is continue oscillation wake - up from sleep mode (1) wdt time out (2) external interrupt (3) /reset pull low all these cases will reset controller , and run the program at address zero. the status just like the power on reset. be sure to enable circuit at case (1) or (2). wake - up from idle mode (1)wdt time out (2) external interrupt (3) internal interrupt like counters all these cases, user has to enable circuit before entering idle mode. after wake - up, all the register will kee p values just like into "slep" instruction before. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 21 at case (2) or (3), controller will wake up and jump to address 0x08 for interruption sub - routine. after finishing sub - routine ("reti" instruction), program will jump to the next instruction from "slep" in struction. vii.7 interrupt rd,re,rf is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. vii.8 instruction set instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register. the symbol "r" represents a register designator which specifies which one of the 64 registers (including operational registers a nd general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "r'', affected by the operation . "k'' represents an 8 or 10 - bit constant or literal value. instruction binary hex mnemonic operation status affected instruction cycle 0 0000 0000 0000 0000 nop no operation none 1 0 0000 0000 0001 0001 daa decimal adjust a c 1 0 0000 0000 0010 0002 contw a ? cont none 1 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 1 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 1 0 0000 0000 rrrr 000r iow r a ? iocr none 1 0 0000 0001 0000 0010 eni enable interrupt none 1 0 0000 0001 0001 0011 disi disable interrupt none 1 0 0000 0001 0010 0012 ret [top of stack] ? pc none 2 0 0000 0001 0011 0013 reti [top of stack] ? pc enable interrupt none 2 0 0000 0001 0100 0014 contr cont ? a none 1 0 0000 0001 rrrr 001r ior r io cr ? a none 1 0 0000 0010 0000 0020 tbl r2+a ? r2 bits 9,10 do not clear z,c,dc 2 0 0000 01rr rrrr 00rr mov r,a a ? r none 1 0 0000 1000 0000 0080 clra 0 ? a z 1 0 0000 11rr rrrr 00rr clr r 0 ? r z 1 0 0001 00rr rrrr 01rr sub a,r r - a ? a z,c,dc 1 0 0001 01rr rrrr 01rr sub r,a r - a ? r z,c,dc 1 0 0001 10rr rrrr 01rr deca r r - 1 ? a z 1 0 0001 11rr rrrr 01rr dec r r - 1 ? r z 1 0 0010 00rr rrrr 02rr or a,r a r ? a z 1 0 0010 01rr rrrr 02rr or r,a a r ? r z 1 0 0010 10rr rrrr 02rr and a,r a & r ? a z 1 0 0010 11rr rrrr 02rr and r,a a & r ? r z 1 0 0011 00rr rrrr 03rr xor a,r a ? r ? a z 1 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 22 0 0011 01rr rrrr 03rr xor r,a a ? r ? r z 1 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 1 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 1 0 0100 00rr rrrr 04rr mov a,r r ? a z 1 0 0100 01rr rrrr 04rr mov r,r r ? r z 1 0 0100 10rr rrrr 04rr coma r /r ? a z 1 0 0100 11rr rrrr 04rr com r /r ? r z 1 0 0101 00rr rrrr 05rr inca r r+1 ? a z 1 0 0101 01rr rrrr 05rr inc r r+1 ? r z 1 0 0101 10rr rrrr 05rr djza r r - 1 ? a, skip if zero none 2 if skip 0 0101 11rr rrrr 05rr djz r r - 1 ? r, skip if zero none 2 if skip 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n - 1) r(0) ? c, c ? a(7) c 1 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n - 1) r(0) ? c, c ? r(7) c 1 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1) r(7) ? c, c ? a(0) c 1 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1) r(7) ? c, c ? r(0) c 1 0 0111 00rr rrrr 07rr sw apa r r(0 - 3) ? a(4 - 7) r(4 - 7) ? a(0 - 3) none 1 0 0111 01rr rrrr 07rr swap r r(0 - 3) ? r(4 - 7) none 1 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 2 if skip 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 2 if skip 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 1 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 1 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 2 if skip 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 2 if skip 1 00kk kkkk kkkk 1kkk call k pc+1 ? [sp] (page, k) ? pc none 2 1 01kk kkkk kkkk 1kkk jmp k (page, k) ? pc none 2 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1 1001 kkkk kkkk 19kk or a,k a k ? a z 1 1 1010 kkkk kkkk 1akk and a,k a & k ? a z 1 1 1011 kkkk kkkk 1bkk xor a, k a ? k ? a z 1 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none 2 1 1101 kkkk kkkk 1dkk sub a,k k - a ? a z,c,dc 1 1 1110 0000 0001 1e01 int pc+1 ? [sp] 001h ? pc none 1 1 1110 100k kkkk 1e8k page k k - >r5(4:0) none 1 1 1111 k kkk kkkk 1fkk add a,k k+a ? a z,c,dc 1 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 23 viii. data ram there are a total of 256 bytes sizes at data ram for epv6 2 00 chip. on the other hand, display segment data buffers can be stored either in data ram of 256 bytes sizes ( 00h~ 40 h ) or in common registers of bank2 and bank3(20h~3fh). d ata ram address 00h~3 8 h 57 x8 segment data buffers 3 9 h~3 e h 6x8 key scanning data buffers 3 f h sw data register 40 h led data register common registers address 20 bank0~bank3 : common registers 3f (32 x8 for each bank) segment data buffers this buffers store display ram. the display ram stores the data transmitted from an external device to the epv6 2 00 through the serial interface and is assigned addresses as follows, in units of 8 bits: x x h x x h l u lower 4 bits higher 4 bits b0 b3 b4 b7 only t he lower 4 bits of the addresses assigned to seg17 through seg20 are valid and the higher 4 bits are ignored. display memory addresses table: seg1 seg4 seg8 seg12 seg16 seg20 00 hl 00 hu 01 hl 01 hu 02 hl dig1 03 hl 03 hu 04 hl 04 hu 05 hl dig2 06 hl 06 hu 07 hl 07 hu 08 hl dig3 09 hl 09 hu 0a hl 0a hu 0b hl dig4 0c hl 0c hu 0d hl 0d hu 0e hl dig5 0f hl 0f hu 10 hl 10 hu 11 hl dig6 12 hl 12 hu 13 hl 13 hu 14 hl dig7 15 hl 15 hu 16 hl 16 hu 17 hl dig8 18 hl 18 hu 19 hl 19 hu 1a hl dig9 1b hl 1b hu 1c hl 1c hu 1d hl dig10 1e hl 1e hu 1f hl 1f hu 20 hl dig11 21 hl 21 hu 22 hl 22 hu 23 hl dig12 24 hl 24 hu 25 hl 25 hu 26 hl dig13 27 hl 27 hu 28 hl 28 hu 29 hl dig14 2a hl 2a hu 2b hl 2b hu 2c hl dig15 2d hl 2d hu 2e hl 2e hu 2f hl dig16 30 hl 30 hu 31 hl 31 hu 32 hl dig17 33 hl 33 hu 34 hl 34 hu 35 hl dig18 36 hl 36 hu 37 hl 37 hu 38 hl dig19 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 24 key scanning data buffers : seg1/ks1 seg2/ks2 seg3/ks3 seg4/ks4 seg5/ks5 seg6/ks6 seg8/ks8 seg7/ks7 seg11/ks11 seg12/ks12 seg10/ks10 seg9/ks9 key1 key2 key3 key4 the key matrix is of 12 x 4 configuration, as show upper . the data of each key is stored as illustrated below, and is read by a read command, starting from the least significant bit. key1?.key4 key1?.key4 seg1/ks1 seg2/ks2 seg3/ks3 seg4/ks4 seg5/ks5 seg6/ks6 seg7/ks7 seg8/ks8 seg9/ks9 seg10/ks10 seg11/ks11 seg12/ks12 b0 -- -- b3 b4 -- -- b7 whe n the most significant bit of data (seg12 b7) has been read, the least significant bit of the next data (seg1 b0) is read. commands a command sets the display mode and status of the vfd driver. the first 1 byte (b0 to b7) inputted to the epv6 2 00 through the din pin after the stb pin has fallen is regarded as a command, and stb pin has fallen will occur interrupt event. if stb is mode high while a command/data is transmitted, serial communication is initialized, and the command/data being t ransmitted is i nvalid (however, the command/data already transmitted remains valid). (1) display mode setting command [00] this command initializes the epv6 2 00, selects the number of segments and number of grids (1/8 to 1/19 - duty, 9 segments to 20 segments). when this c ommand is executed, display is forcibly turned off, and key scanning is also stopped. to resume display, a display on command must be executed. if the same mode is selected, however, nothing is performed. when power is turned ?on?. display mode: 19 - digit , 9 - segment. reading sequence EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 25 not relevant display mode 0000 : 8 digits, 20 segments. 000 1 : 9 digits, 19 segments. 001 0 : 10 digits, 18 segments. 0011 : 11 digits, 17 segments. 1000 : 12 digits, 16 segments. 1001 : 13 digits, 15 segments. 101 0 : 14 digits, 14 segments. 1011 : 15 digits, 13 segments. 1100 : 16 digits, 12 segments. 1101 : 17 digits, 11 segments. 111 0 : 18 digits, 10 segments. 1111 : 19 digits, 9 segments. 0 0 0 0 1 1 1 1 initial value msb lsb b7 b6 b5 b4 b3 b2 b1 b0 (2) data setting command [01] this command sets data write and data read modes. when power is turned ?on?. address increment mode: address increment mode. mode setting: normal operation mode. b3 initial value b5 0 b7 0 msb 0 b0 0 0 b2 0 b4 0 b6 1 b1 lsb sets address increment mode (display 0 : increments address after data has been 1 : fixes address. sets test mode 0 : normal 1 : test mode. 01 : write data to led 00 : write data to display memory . 10 : read key port switch data 11 : read switch status. data write & read mode EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 26 (3) display control command [10] when power is turned ?on?. 4 /6 4 - pulse width is set and the display is turned off.. key & switch scanning is stopped. 0 msb b4 1 initial value 0 0 b6 b1 0 b3 0 b0 lsb 0 b5 b2 0 b7 sets dimming quantity. 00 0 : sets pulse width to 1/ 1 6 0 0 1 : sets pulse width to 2 / 1 6 0 10 : sets pulse width to 4 / 1 6 0 11 : sets pulse width to 10 / 1 6 100 : sets pulse width to 11 / 1 6 101 : sets pulse width to 12 / 1 6 110 : sets pulse width to 13 / 1 6 111 : sets pulse width to 14 / 1 6 turns on/off display. 0 : display off (key & switch scan continues) 1 : display on. (4) address setting command [11] this command sets an address of the display memory when power is turned ?on?, the address is set to 00h. 0 msb b4 1 initial value 0 0 b6 b1 0 b3 1 b0 lsb 0 b5 b2 0 b7 address ( 00h - 38h ) if address 3 9 h or higher is set, the data is ignored, until a correct address is set. EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 27 viii. rc/crystal osc (i) general description this oscill ator is designed for the epv6 200 chip as clock source. ( ii ) feature l rc oscillator: 32.768 k hz l operating voltage: 2.2 ~5.5v. l operating temperature: - 20 o c ~ 7 0 o c (iii) block diagram xout vdd xin 470k (iv) pin description name i/o type descripti on note xin i crystal or rc oscillator connection pin xout o crystal oscillator output pin vdd - power supply (+) pin vss - power supply ( - ) pin (v) electrical ( condition : vdd = 4.5 to 5.5v, ta = - 20 c to 70 c ) parameters sym. min. typ. max. unit conditions starting oscillation voltage vs - 2.0 3.2 v stable time ts - 5 10 clk vdd = 5.0v current consumption idd - 2 3 ma vdd = 5.0v duty cycle 45 50 55 % frequency/voltage deviation ? f/ ? v - 1 1.5 % frequency/temperature deviation d f - 1 2 % frequency v.s. process deviation - 6 10 % ix. absolute operation maximum ratings absolute maximum ratings (ta = 25 c, vss = 0 v) parameter symbol ratings unit logic supply voltage v dd - 0.5 to + 6 v driver supply voltage v ee vdd +0.5 to vdd - 45 v logic input voltage v i - 0.5 to vdd +0.5 v vfd driver output voltage v o vee - 0.5 to vdd +0.5 v led driver output current i o1 +25 ma vfd driver output current i o2 - 40 (grid) - 15 (segment) ma operating ambient temperature t opt - 40 to +85 c storage temperature t stg - 65 to +150 c EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 28 i ix. dc electrical characteristic (ta = - 20 to +70 c, v dd = 4 .5 to 5.5v, vss = 0v, v ee = v dd - 45v) parameter symbol min. typ. max. unit test conditions digital input voltage high v i h 0.8v dd - v dd v digital input voltage low i ol v ss - 0.2v dd v gpio b schmitt trigger negative going threshold voltage v t - 1.5 1.8 2.1 schmitt trigger positive going threshold voltage v t+ 2.9 3.2 3.5 v gpioc, gpo9 , clk , stb, din and /reset pull up resister r pu 50 75 100 k [ gpioc, gpo9 , clk , stb, dout, din , cryxrc and /reset @ vdd= 5v , digital output voltage high v oh 0.8v dd - v dd v digital output voltage low v ol v ss - 0.2v dd v dout, gpiob, gpioc digital output high current i oh1 - 2 - 3 - 4 ma v oh =2.4v / dout, gpioc digi tal output low current i ol1 2 3 4 ma v ol =0.4v / dout, gpioc digital output high current i oh2 - 15 - 18 - 20 ma v oh =2.4v / gpio9 digital output low current i ol2 15 18 20 ma v ol =0.4v / gpio9 hv output current i oh1 - 3 - 2.7 - 2.4 ma vo = vdd ? 2v, (vdd=5v) seg1/k s1 to seg6/ks6, sg7 to sg11 hv output current i oh2 - 15 - 14 - 12 ma vo = vdd ? 2v, (vdd=5v) gr1 to gr6, gr7/sg16 to gr 11 /sg12, hv leakage current i hv leak 5 8 10 ua vo = vdd ? 40 v, driver off hv output pull - down resistor r l 50 100 150 k w driver output power down current (sleep mode) i sb1 - 1 m a all input and i/o pin at vdd, output pin floating, wdt disabled low clock current (green mode) i sb2 35 50 m a clk=32.768khz, all analog circuits disabled, all input and i/o pin at vdd, output low clock current (idl e mode) i sb3 30 45 m a clk=32.768khz, all analog circuits disabled, all input and i/o pin at vdd, output operating supply current (normal mode) i cc 1.3 2 ma /reset=high, clk=3.582mhz, all analog circuits disabled, output pin floating EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 29 ii x. ac electrica l characteristic cpu instruction timing (ta = - 20 c ~ 70 c, v dd =5v, v ss =0v) parameter symbol condition min typ max unit input clk duty cycle dclk 45 50 55 % instruction cycle time tins 32.768khz 3.582mhz 60 550 us ns device delay hold time tdrh 16 ms tcc input period ttcc note 1 (tins+20)/n ns watchdog timer period twdt ta = 25 c 16 ms note 1: n= selected prescaler ratio. timing characteristic (vdd=5v,ta=+25 c) description symbol min typ max unit oscillator timing characteristic osc star t up 32.768khz tosc 400 1500 ms 3.579mhz pll 5 10 us spi timing characteristic (cpu clock 3.58mhz and fsco = 3.58mhz /2) /ss set - up time tcss 560 ns /ss hold time tcsh 250 sclk high time thi 250 ns sclk low time tlo 250 ns sclk rising t ime tr 15 30 ns sclk falling time tf 15 30 ns sdi set - up time to the reading edge of sclk tisu 25 ns sdi hold time to the reading edge of sclk tihd 25 ns sdo disable time tdis 560 ns EPV6200 operation voltage(x axis min vdd ; y axis main clk): 5.5 4 3.6 17.91 mhz v 14.33 10.74 3.0 2.5 7.16 3.58 1.79 2.2 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 30 ii ix . timing diagrams fig. ac timing ins EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 31 key & switch scanning and display timing the key & switch scanning and display timing diagram is given below. one cycle of key & switch scanning consists of 2 frames. the data of the are 12 x 4 matrix is stored in the ram. grid 1 grid 2 grid 3 grid n key & switch scan data dig1 2/16 grid 1 output 1 frame = t disp * (n+1) disp ? 500us 2/16 seg1 output seg2 output seg3 output segn output 14/16 grid 2 output grid 3 output grid n output 1/16 4/16 10/16 EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 32 serial or parallel communication format reception (command/data write) b0 b1 b2 b6 b7 din stb 1 2 3 7 8 clk if data is contiguous transmission (data read) b0 b1 b2 b3 b4 b5 b6 b7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 stb din clk b0 b1 b2 b3 b4 b5 dout * t wait data reading command is set. data reading starts. when data is read, a wait time t wait of is necessary between the rising of the eighth clock that has set t he command and the falling of the first clock that has read the data. the wait time is adjustable according to different application . . EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 33 switching characteristic waveform f osc 50 % osc stb clk data in data out sn/gn pw pw pw t t t t t t t 90% 10% clk clk clk stb stb setup hold pzl plz thz tzh switching characteristics (ta = - 20 to + 70 c, vdd = 4.5 t o 5. 5 v, vee = vdd - 45 v) parameter symbol min. typ. max. unit test conditions oscillation frequency t osc - 32.768 - khz propagation delay t plz - - 300 ns clk ? dout time t pzl - - 100 ns cl = 15pf, rl = 10k w rise time t tzh1 2 us cl = 300pf seg1/ks1 t o seg4/ks4, sg5/ks5 to sg9/ks9. t tzh2 0.5 us gr1 to gr8 gr9 /sg20 to gr9 /sg13, gr17/ sg12/ks12 to gr19 /sg10/ks10 fall time t thz 100 110 120 us cl = 300pf, segn, gridn data input clock freq. f max - 1 1.25 mhz duty = 50 % , clk input capacitance c i 15 pf clock pulse width pw clk 400 500 - ns storbe pulse width pw stb 0.8 1 - us data setup time t setup 100 - - ns data hold time t hold 100 - - ns clock - strobe time t clkstb 0.8 1 - us clk - ? stb - wait time t wait - 3 - us clk - ? clk - * EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 34 serial i/f s ets display data sequence: updating display memory by incrementing address stb clk data input command1 command2 command3 command4 data 1 data n command 1: display mode. command 2: sets data. command 3: sets address. data 1 to n: transfers display data. ( 57 bytes max.) command 4: controls display. updating specific address data data input command2 stb clk data n command1 command3 command 1: sets data. command 2: sets address. data: display data EPV6200 vfd controller this specification is subject to change without further notice. 04 /06/200 4 ( v 1 .2) 35 xi i i. application vfd controller for dvd player servo controller rf front - end back - end sdram mmu x86/51 /risc apu vpu bitstream flash epv6300 vfd controller 4 stb,din,dout,clk ir vfd controller for dvd r/w dvd/dvr EPV6200 EPV6200 spi din ,dout ,clk,stb grid 28 segment EPV6200 spi 28 i/o 4 spi 1 g~19g 27 s~8s 4 4 |
Price & Availability of EPV6200
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |